This nonprovisional application claims priority under 35 U.S.C. xc2xa7 119(a) on Patent Application No. 2002-019138 filed in JAPAN on Jan. 28, 2002, which is herein incorporated by reference.
The present invention relates to a D/A converter circuit for converting an input digital signal into an analog signal, which adopts an R-2R ladder resistor-net, and in particular to a two-stage D/A converter circuit realizing resolution enhancement by two-stage D/A conversion operation.
A D/A (digital-analog) converter having an R-2R ladder resistor-net is a circuit for converting an input digital signal into an analog signal and outputting the converted signal. For example, the D/A converter is made up of a resistor-net 71 including a resistor having resistance value of R and a resistor having resistance value of 2R (series resistance value of R and R), a group of switches 73 connected to the resistor-net 71 and an offset level control resistor 72, as with an R-2R ladder resister type D/A converter 70 shown in FIG. 8. FIG. 8 shows an example of 3-bit input, and digital input signals D3, D4 and D5 are respectively inputted to switches SW3, SW4 and SW5 making up the group of switches 73. The digital input signal D3 is MSB (Most Significant Bit) and the digital input signal D5 is LSB (Least Significant Bit). An offset terminal OFFCR is provided on an end of the offset level control resistor 72.
The following will more specifically explain operation principle of the R-2R ladder resistor type D/A converter 70 with reference to FIG. 8. The switches SW 3 through SW5 of the group of switches 73 control input to the resistor-net 71 according to the digital input (D3 through D5) by switching the input to Vdd when the digital input is HIGH, and switching the input to Gnd when the digital input is LOW. Thus, with the input of the digital input signals D3 through D5, an analog output voltage Aout can be expressed by the following equation:
Aout={(D3xc3x9722+D4xc3x9721+D5xc3x9720)/23}Vdd+offset 
Here, Dn (n=3, 4, 5) is 0 or 1 (depending on the digital input code). The offset varies depending on the voltage inputted to the offset terminal OFFCR.
As shown in FIG. 9(a), when Gnd is inputted to the offset terminal OFFCR, the analog output becomes Gnd to (Vddxe2x88x921LSB), and as shown in FIG. 9(b), when Vdd is inputted to the offset terminal OFFCR, the analog output becomes (Gnd+1LSB) to Vdd. Further, as shown in FIG. 9(c), when the intermediate voltage value between Gnd and Vdd is inputted to the offset terminal OFFCR, the analog output becomes the intermediate value between FIG. 9(a) and FIG. 9(b).
The R-2R ladder resistor type D/A converter 70 outputs the analog output Aout according to the foregoing equation when the ratio of R to 2R is accurately 1:2. However, as it is clearly shown in FIG. 8, due to ON resistance of the switches SW3 through SW5, 2R actually becomes 2R+xcex1 (xcex1 is ON resistance of the switches). Therefore, in order to compensate the ratio of R side to 2R side to be 1:2, for example, Japanese Laid-Open Patent Application Tokukaisho 64-042924/1989 (published on Feb. 15, 1989), Japanese Laid-Open Patent Application Tokukaihei 02-013014/1990 (published on Jan. 17, 1990), Japanese Laid-Open Patent Application Tokukaihei 02-202227/1990 (published on Aug. 10, 1990), Japanese Laid-Open Patent Application Tokukaihei 04-138725/1992 (published on May 13, 1992) or some other publications disclose an arrangement for always turning on switches also in the R side. Note that, it is also possible to provide the resistance value of 2R side by originally subtracting by ON resistance of the switches so as to compensate the ratio of 1:2. Further, Japanese Laid-Open Patent Application Tokukaihei 03-77430/1991 (published on Apr. 3, 1991) discloses an arrangement for switching the voltage inputted to the input terminal of the offset level control resistor between the upper limit voltage and the lower limit voltage inputted to the input terminal of 2R side. This arrangement realizes a D/A converter with high resolution and high accuracy even without improving accuracy of resistance element.
Here, as the R-2R ladder resistor type D/A converter 70 in FIG. 8 reveals, in the R-2R ladder resistor type D/A converter, the required number of the unit resister R is calculated as 3n+1 with respect to the bit number n of the digital input signal. Accordingly, the R-2R ladder resistor type D/A converter requires smaller area for resistors compared to a binary resistor type D/A converter (the number of unit resistor is 2nxe2x88x921 with respect to the bit number n), and besides, a D/A converter with high performance can be realized by ensuring only the relative accuracy for the accuracy of the resistor even without ensuring the absolute value. Thus, this mode is advantageous when using as an IC.
However, the relative accuracy between resistors used for the ladder resistor-net in the R-2R ladder resistor type D/A converter is merely about 0.05% without trimming. For this reason, it is difficult to constitute a D/A converter of 10 bits or above only by the R-2R ladder resistor type D/A converter.
In order to increase resolution without costly trimming, two-stage D/A conversion (plural-stages in general) may be performed as with the two-stage D/A converter circuit 90 shown in FIG. 10. The two-stage D/A converter circuit 90 includes a first stage D/A converter 91, a second stage R-2R ladder resistor type D/A converter 92, a latch circuit 93 and a reference voltage generation circuit 94.
The latch circuit 93 latches digital input data Din in accordance with a clock signal CK, and upper m bit of the latched digital input data Din is inputted to the first stage D/A converter 91 performing first D/A conversion of the two-stage conversion. The first stage D/A converter 91 generates an analog output voltage according to the upper m bit and an analog output voltage according to digital input of the upper m bit+1 from reference voltages VH and VL inputted from the reference voltage generation circuit 94, and then outputs the voltages respectively as a reference voltages VL and a reference voltage VH.
Further, lower n bit of the latched digital input data Din is inputted to the second stage R-2R ladder resistor type D/A converter 92 performing second D/A conversion of the two-stage conversion. Further, the second stage R-2R ladder resistor type D/A converter 92 generates a final analog signal Aout of the digital input data Din based on the reference voltages VL and VH inputted from the first stage D/A converter 91, and the lower n bit, then outputs the analog signal Aout. The second stage R-2R ladder resistor type D/A converter 92 is made of the R-2R ladder resistor type D/A converter shown in FIG. 8, and the reference voltage VH, and the reference voltage VL are inputted respectively instead of Vdd and GND of FIG. 8.
The following will explain a resistor string type (also referred to as voltage potentiometer type) D/A converter 91a shown in FIG. 11 as an example of the first stage D/A converter 91. FIG. 11 shows an example in which the upper bit of the digital input data Din is 3 bits, i.e., the input and output is carried out in eight-stages. The resistor string type D/A converter 91a includes a resistor string 101, reference voltage switches 102 and 103, an upper limit reference voltage VH buffer amp 104 and a lower limit reference voltage VL buffer amp 105.
The resistor string 101 is a voltage dividing circuit made up of resistors r0 through r7 connected in series, and the reference voltage VH is inputted to an end of the resistor r0 side and the reference voltage VL is inputted to an end of the resistor r7 side. The reference voltage switch 102 includes switches SH0 through SH7. These switches are respectively used for sequentially inputting a voltage in an end of reference voltage VH input side of the resistors r0 through r7 to the upper limit reference voltage VH buffer amp 104. Further, the reference voltage switch 103 includes switches SL0 through SL7. These switches are respectively used for sequentially inputting a voltage in an end of reference voltage VL input side of the resistors r0 through r7 to the lower limit reference voltage VL buffer amp 105. The respective switches are opened/closed by a control signal according to the result of decoding of the upper 3 bits by a decoder (see FIG. 10) inside of the first stage D/A converter 91.
The upper limit reference voltage VH buffer amp 104 outputs a voltage inputted via one of the switches included in the reference voltage switch 102 as the upper limit reference voltage VH. Further, the lower limit reference voltage VL buffer amp 105 outputs a voltage inputted via one of the switches included in the reference voltage switch 103 as the lower limit reference voltage VL.
In the resistor string type D/A converter 91a having the foregoing arrangement, when the upper 3 bits of the digital input data Din are xe2x80x9c111xe2x80x9d, for example, the switches SH0 and SL0 are turned on, and the respective voltages in both ends of the resistor r0 are outputted as the upper limit reference voltage VH and the lower limit reference voltage VL. Further, when the upper 3 bits are xe2x80x9c110xe2x80x9d, the switches SH1 and SL1 are turned on, and the respective voltages in both ends of the resistor r1 are outputted as the upper limit reference voltage VH and the lower limit reference voltage VL. For the rest, the upper limit reference voltage VH and the lower limit reference voltage VL corresponding to each resistor are outputted by operating those switches in accordance with the digital inputs down to the upper 3 bits of xe2x80x9c000xe2x80x9d.
However, respective output voltages from the upper limit reference voltage VH buffer amp 104 and the lower limit reference voltage VL buffer amp 105 used in this case generally include offset component due to dispersion of the input transistor of the buffer amp. Therefore, as shown in FIG. 12, when the upper bit is switched in the resistor string type D/A converter 91a, a discontinuity may occur at a border of the range of analog output voltage. Accordingly, for the use requiring uniformity and continuity, a resistor string type D/A converter 91b shown in FIG. 13 designed for solving the foregoing problem by having a different type of switch connection is used.
The resistor string type D/A converter 91b shown in FIG. 13 includes a resistor string 111, a reference voltage switch 112, a reference voltage VH buffer amp 113 and a reference voltage VL buffer amp 114. The resistor string 111 has the same configuration as that of the resistor string 101 of FIG. 11. The reference voltage switch 112 includes switches SH0 through SH7 and switches SL0 through SL7, and a single switch operates as the switch SLk and the Switch SH (k+1) (k=0, 1, 2 . . . 6). The switches SH0, SH2 (SL1), SH4 (SL3), and SH6 (SL5) respectively operate to sequentially input a voltage in an end of reference voltage VH input side of the resistors r0, r2, r4, r6 to the reference voltage VH buffer amp 113, and, the switch SL7 operates to input a voltage in an end of reference voltage VL input side of the resistor r7 to the reference voltage VH buffer amp 113. Meanwhile, the switches SH1 (SL0), SH3 (SL2), SH5 (SL4), and SH7 (SL6) respectively operate to sequentially input a voltage in an end of input side of reference voltage VH of the resistors r1, r3, r5, r7 to the reference voltage VL buffer amp 114. The respective switches are opened/closed by a control signal according to the result of decoding of the upper 3 bits by a decoder (see FIG. 14) inside of the resistor string type D/A converter 91b. 
The reference voltage VH buffer amp 113 outputs a voltage inputted via the reference voltage switch 112 as the reference voltage VH, and the reference voltage VL buffer amp 114 outputs a voltage inputted via the reference voltage switch 112 as the reference voltage VL.
In the resistor string type D/A converter 91b having the foregoing arrangement, when the upper 3 bits of the digital input data Din are xe2x80x9c111xe2x80x9d, for example, the switches SH0 and SL0 (SH1) are turned on so as to output the respective voltages in both ends of the resistor r0 as the reference voltage VH and the reference voltage VL. Further, when the upper 3 bits are xe2x80x9c110xe2x80x9d, the switches SH1 (SL0) and SL1 (SH2) are turned on so as to output the respective voltages in both ends of the resistor r1 as the reference voltage VH and the reference voltage VL. For the rest, the reference voltage VH and the reference voltage VL corresponding to each resistor are outputted by operating those switches in accordance with the digital inputs down to the upper 3 bits of xe2x80x9c000xe2x80x9d. As a result, the discontinuity does not occur at the border of the range of analog output voltage when the upper bit is switched in the resistor string type D/A converter 91b. 
Here, the resistor string type D/A converter 91b differs from the resistor string type D/A converter 91a of FIG. 11 in the following point. In the resistor string type D/A converter 91a, the reference voltage VH is always outputted with higher voltage level than the reference voltage VL; in contrast, in the resistor string type D/A converter 91b, the voltage levels of the reference voltage VH and the reference voltage VL alternately become high or low according to the digital input. Therefore, the two-stage D/A converter using the resistor string type D/A converter 91b of FIG. 13 additionally includes an exchanger 122 as with the two-stage D/A converter circuit 121 shown in FIG. 14.
The exchanger 122 outputs the reference voltage VH and the reference voltage VL to the second stage R-2R ladder resistor type D/A converter 92 respectively as the upper limit reference voltage VHH and the lower limit reference voltage VLL when the reference voltage VH is higher in the voltage level than the reference voltage VL. Further, when the reference voltage VH is lower in the voltage level than the reference voltage VL for the reason above, the exchanger 122 outputs the reference voltage VL as the upper limit reference voltage VHH, and outputs the reference voltage VH as the lower limit reference voltage VLL so as to use these voltages as the reference voltage of the second stage R-2R ladder resistor type D/A converter 92. The judgments of those voltage levels and whether or not the reference voltage levels are actually swapped are controlled by a control signal CE showing the voltage level relation between the reference voltage VH and the reference voltage VL. The control signal CE is generated as a result of decoding of the upper 3 bits by the resistor string type D/A converter 91b. 
The exchanger 122 is generally made up of some switches such as the switches SW11, SW12, SW13 and SW 14 shown in FIG. 15(a). In FIG. 15(a), the control signal CE is inputted to the switches SW11 and SW14, and an inversion signal CEb of the control signal CE is inputted to the switches SW12 and SW13. These switches are controlled so that the switches 12 and 13 become OFF (closed)-state when the switches SW11 and SW14 are in ON (opened)-state, and the switches 12 and 13 become ON-state when the switches SW11 and SW14 are in OFF-state. Further, the inversion signal CEb is generated after the control signal CE passes through the inverter 131, as shown in FIG. 15(b).
For example, xe2x80x98xe2x80x9cINTEGRATED ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERSxe2x80x9d, pp233-234, Kluwer Academic Publishers, 1994xe2x80x99 describes the foregoing two-stage D/A converter circuit in which the voltage levels of the reference voltage VH and the reference voltage VL alternately become high or low so that the reference voltages VH and VL are outputted as the reference voltages of the second stage D/A converter.
Incidentally, in the described two-stage D/A converter circuit, i.e., the two-stage D/A converter circuit using the R-2R ladder resistor type D/A converter as the second stage converter, since the exchanger includes a plurality of switches, ON resistance of the respective switches may vary due to manufacturing variation of the switches. Thus, even when the reference voltage VH has a uniform voltage level, output voltage level of the exchanger may vary depending on which switch is in ON-state, for example, the output voltage level respectively differ in the case of outputting the voltage as an upper limit reference voltage VHH via SW 11 of FIG. 15(a), and in the case of outputting the voltage as a lower limit reference voltage VLL via SW12.
Further, due to ON resistance (xcex1) of the switches of the exchanger, resistance value of 2R side in the second stage R-2R ladder resistor type D/A converter becomes 2R+xcex1, and therefore resistance ratio of R to 2R fluctuates. This may cause inaccurate operation of the D/A converter, depending on the value of xcex1.
As described, a conventional two-stage D/A converter circuit could cause a problem of degrading D/A conversion accuracy of the second stage n bit R-2R ladder resistor type D/A converter, which causes degradation of D/A conversion accuracy of the whole two-stage D/A converter circuit. Accordingly, the conventional two-stage D/A converter circuit causes a problem of a difficulty in ensuring uniformity and continuity of output analog voltage value.
An object of the present invention is to provide a D/A converter circuit carrying out (m+n) bits D/A conversion by generating two kinds of reference voltages, which are used in a second n bit R-2R ladder resistor type D/A converter, by a m bit D/A converter, and capable of easily ensuring uniformity and continuity, and further capable of obtaining high D/A conversion accuracy; and also to provide a portable terminal device and an audio device having the D/A converter circuit.
In order to attain the foregoing objects, the D/A converter circuit of the present invention includes: a first D/A converter for generating a first reference voltage and a second reference voltage different to each other in voltage level according to upper m bit of digital input data of (m+n) bits; a second D/A converter of R-2R ladder resistor type for converting the digital input data to an analog voltage value by using information of lower n bit of the digital input data and the first and second reference voltages so that the analog voltage value is within a range whose upper limit is a higher voltage level of the first reference voltage and the second reference voltage, and whose lower limit is a lower voltage level of the first reference voltage and the second reference voltage, the first reference voltage being supplied to respective input terminals on digital data input side of a ladder resistor-net in the second D/A converter when each bit of digital data of the lower n bit inputted to the second D/A converter has a first value, and the second reference voltage being inputted to the respective input terminals on the digital data input side of the ladder resistor-net in the second D/A converter when each bit of the digital data of the lower n bit supplied to the second D/A converter has a second value; controlling means for generating a control signal according to which of voltage levels of the first reference voltage and the second reference voltage is higher; and inverting means for inputting the digital data of the lower n bit as such to the second D/A converter when the control signal shows that the first reference voltage is higher in voltage level than the second reference voltage, and inputting the digital data of the lower n bit to the second D/A converter by exchanging the first value and the second value of the digital data of the lower n bit when the control signal shows that the first reference voltage is lower in voltage level than the second reference voltage.
With the foregoing arrangement, the provided first D/A converter generates the first and second reference voltages of different voltage levels that are according to the upper m bit of the digital input data of (m+n) bits. The first D/A converter inputs the first and second voltages to the second D/A converter of an R-2R ladder resistor type. The controlling means generates a control signal according to which of voltage levels of the first reference voltage and the second reference voltage is higher. Further, the inverting means inputs the digital data of the lower n bit as such to the second D/A converter when the control signal shows that the first reference voltage is higher in voltage level than the second reference voltage, and inputs the digital data of the lower n bit to the second D/A converter by exchanging the first value and the second value of the digital data of the lower n bit when the control signal shows that the first reference voltage is lower in voltage level than the second reference voltage.
With the foregoing operation by the inverting means, when the digital data is supplied to respective input terminals on digital data input side of a ladder resistor-net in the second D/A converter by the inverting means, the reference voltage of higher voltage level is supplied to respective input terminals on digital data input side of a ladder resistor-net in the second D/A converter when each bit of digital data of the lower n bit inputted to the second D/A converter has a first value, and the second reference voltage is inputted to the respective input terminals on the digital data input side of the ladder resistor-net in the second D/A converter when the bit of the digital data of the lower n bit supplied to the second D/A converter has a second value regardless of which of voltage levels of the first and second reference voltages is higher. Further, the second D/A converter uses information of lower n bit, i.e., the digital data inputted from the inverting means and the first and second reference voltages so as to convert the digital data into an analog voltage value so that the analog voltage value is within a range whose upper limit is a higher voltage level of the first reference voltage and the second reference voltage, and whose lower limit is a lower voltage level of the first reference voltage and the second reference voltage.
On this account, D/A conversion can be carried out by using the second D/A converter without using such as an exchanger even with the first D/A converter in which the voltage levels of the first reference voltage and the second reference voltage become alternately high or low according to the upper m bit. Consequently, higher D/A conversion accuracy can be obtained since the exchanger including a plurality of switches is not required.
As a result, it is possible to provide a D/A converter circuit carrying out (m+n) bits D/A conversion by generating two kinds of reference voltages, which are used in a second n bit R-2R ladder resistor type D/A converter, by a m bit D/A converter, and also capable of easily ensuring uniformity and continuity of the output analog voltage value, and further capable of obtaining high D/A conversion accuracy.
Further, in order to attain the foregoing objects, a portable terminal device of the present invention includes one of the described D/A converter circuits.
With the foregoing arrangement, uniformity and continuity of the output analog voltage value can be ensured and also high D/A conversion accuracy can be obtained at a portion carrying out D/A conversion, such as a control voltage generation circuit at an Analog Front End in a portable terminal device.
Further, the foregoing D/A converter circuit 10 can also be used as a volume control circuit of an audio device. On this account, high D/A conversion accuracy can be obtained which ensures uniformity and continuity of the output analog voltage value at a portion carrying out D/A conversion in the volume control circuit.
Further, in order to attain the foregoing objects, an audio device of the present invention includes one of the described D/A converter circuits.
With the foregoing arrangement, uniformity and continuity of the output analog voltage value can be ensured and also high D/A conversion accuracy can be obtained at a portion at a portion carrying out D/A conversion, such as a volume control circuit.
Additional objects, features, and strengths of the present invention will be made clear by the description below. Further, the advantages of the present invention will be evident from the following explanation in reference to the drawings.